Masked ROMs with NOR-type memory cell arrays in which bit lines are constructed in a hierarchical arrangement have been disclosed in "16Mb ROM Design Using Bank Select Architecture," Symposium on VLSI Circuits, pp.85-88, Aug. 1988. In the technique disclosed in the a fore-mentioned article, the reading-out process is accomplished through three steps: precharging main bit lines to predetermined voltage levels; sensing a voltage level of a main bit line to determine whether a selected memory cell is an on-cell or an off-cell; and outputting data detected from the selected memory cell to the output of the memory device. Referring to FIG. 1, in order to sense data stored in a memory cell of a memory block, a pair of bank selection lines BS1 and BE2 are activated to select main bit line MB5, and a power supply voltage is applied to word line WL0 connected to the selected memory cell M81. The voltage level designating a data bit from memory cell M81 is detected in sense amplifier SA5, in accordance with the state of current flowing through the selected memory cell. If the selected memory cell M81 is an on-cell, a voltage level at the corresponding main bit line MB5 is lowered under the precharged level. On the other hand, if the selected memory cell is an off-cell, the precharged level of the main bit line MB5 is maintained therein.
However, in the case where: the selected memory cell M81 is an on-cell; M41 corresponding to main bit line MB3 is an off-cell; and M51, M61 and M71 are all on-cells; then, since the bank selection lines BS1 and BE2 are enabled and word line WL0 is activated, a current path through the channels of M51, M61 and M71 is formed such that current is poured into sub bit line SBL8, thereby disturbing the sensing current on sub bit line SBL9 connected to main bit line MB5. This disturbance, due to the current from the on-cells M51 through M71 results in a malfunction in detecting the state of the selected memory cell M81. M81 may be regarded to as an off-cell because the voltage level of the main bit line MB5 can not be lowered due to the disturbance of flowing current.
Furthermore, assuming that the selected memory cell M81 is an off-cell and adjacent memory cells M91, M101 and M111 are all on-cells, leakage current through the adjacent on-cells is formed to degrade the sensing stability for the selected memory cell M81. As a result, whatever the state of the selected memory cell is, the performance in sensing the memory cell may be degraded.